1. Field of the Invention
The present invention relates to a power supply voltage detection circuit.
2. Description of Related Art
The operation of an electronic circuit, which operates mainly with a direct current, is not stable at low voltage until a power supply voltage reaches the operation guaranteed range. Thus, the output of the electronic circuit is indefinite at low voltage. Then an excessive current flows into the electronic circuit or a device connected to a subsequent stage. Therefore, a failure such as a destruction of these circuits occurs at worst. In order to avoid such failure, an electronic circuit usually has a power supply voltage detection circuit mounted therein. The power supply voltage detection circuit outputs a control signal at low voltage so as not to operate the electronic circuit. This method is generally called UVLO (Under Voltage Lock Out).
Japanese Unexamined Patent Application Publication No. 2007-258530 discloses the technique concerning such power supply voltage detection circuit. FIG. 7 illustrates a low voltage detection circuit (power supply voltage detection circuit) disclosed in Japanese Unexamined Patent Application Publication No. 2007-258530. A low voltage detection circuit 510 illustrated in FIG. 7 is provided with N-channel MOS transistors 531, 533, and 538, resistors 532, 536, 537, and 540, a diode 534, a Zener diode 535, and an inverter 539.
In FIG. 7, an input terminal 511 supplied with an input voltage (power supply voltage VDD) is connected to a drain of the N-channel MOS transistor 531 and one terminal of the resistor 532. The other terminal of the resistor 532 is connected to a gate of the N-channel MOS transistor 531 and a drain of the N-channel MOS transistor 533. A source of the N-channel MOS transistor 533 is grounded. A source of the N-channel MOS transistor 531 is connected to an internal power supply terminal, an auxiliary power supply terminal 516, and an anode side of the diode 534. A cathode side of the diode 534 is connected to a cathode side of the Zener diode 535. An anode side of the Zener diode 535 is connected to a gate of the N-channel MOS transistor 533. An anode side of the Zener diode 535 is grounded via the resistors 536 and 537.
A gate of the N-channel MOS transistor 538 is connected to a junction of the resistors 536 and 537. A source of the N-channel MOS transistor 538 is grounded. Then, a drain of the N-channel MOS transistor 538 is connected to the low voltage detection terminal 523 via the inverter 539. The drain of the N-channel MOS transistor 538 is also connected to a reference voltage terminal 522, which is supplied with the reference voltage via the resistor 540.
First, a case in which the input voltage VDD is low at the time of power on is explained. In this case, a voltage is applied to the gate of the N-channel MOS transistor 531 via the resistor 532. However, this voltage does not reach a threshold voltage Vth1 of the N-channel MOS transistor 531. Thus, the N-channel MOS transistor 531 is turned off. Therefore, the internal power supply voltage 516 indicates 0V. At this time, the gate of the N-channel MOS transistor 538 is also 0V. Accordingly, the N-channel MOS transistor 538 is turned off. Therefore, the voltage by the side of the input terminal of the inverter 539 indicates the reference voltage via the resistor 540. Then, a signal of 0V is output outside from the low voltage detection terminal 523.
Next, a case in which the input voltage VDD further increases is explained. In this case, a voltage more than or equal to the threshold voltage Vth1 is applied to the gate of the N-channel MOS transistor 531 via the resistor 532. Then, the N-channel MOS transistor 531 is turned on. At this time, the internal electrical power supply voltage 516 indicates a voltage, which is the input voltage VDD subtracted by the threshold voltage Vth of the N-channel MOS transistor 531. On the other hand, a gate voltage of the N-channel MOS transistor 538 does not reach a threshold voltage Vth2 by a forward drop voltage VF of the diode 534, a voltage drop by a Zener voltage VZ of the Zener diode 535, and resistors 536 and 537. Then, the N-channel MOS transistor 538 is turned off. Therefore, the voltage by the side of the input terminal of the inverter 539 indicates the reference voltage via resistor 540. Then, a signal of 0V is output from the low voltage detection terminal 523.
Next, a case in which the input voltage VDD further increases is explained. In this case, the gate voltage of the N-channel MOS transistor 538 increases. Then, the N-channel MOS transistor 538 is turned on. Thus, the reference voltage is discharged via the resistor 540 and the N-channel MOS transistor 538. That is, the voltage by the side of the input terminal of the inverter 539 indicates 0V. Then, a high-level signal is output outside from the low voltage detection terminal 523. That is, a signal of the same voltage as the reference voltage is output outside from the low voltage detection terminal 523. The N-channel MOS transistor 533 is to stable the voltage of the internal power supply voltage 516 until the auxiliary power supply voltage 516 rises. As the N-channel MOS transistor 533 is not concerned with the operation of the low voltage detection signal, the explanation is omitted.
FIG. 8 illustrates the relationship between the input voltage VDD and the output voltage. As illustrated in FIG. 8, based on a predetermined voltage value of the input voltage VDD (hereinafter referred to as a detection voltage VOL), the circuit of FIG. 7 outputs a low voltage detection signal of 0V (L level) when the input voltage VDD is lower than the detection voltage VOL, and outputs a low voltage detection signal of the same voltage (H level) as the reference voltage when the input voltage VDD is higher than detection voltage VOL. Thus, the circuit illustrated in FIG. 7 can force to stop the operation of an electronic circuit by the low voltage detection signal, in case of the input voltage VDD with unstable operation.
In order for the low voltage detection circuit illustrated in FIG. 7 to output the low voltage detection signal correctly, the reference voltage needs to be operating normally. However, a circuit for generating the reference voltage (not illustrated and hereinafter referred to as a reference voltage generation circuit) usually generates the reference voltage according to the input voltage VDD. Therefore, the operation of the reference voltage generation circuit is unstable until the input voltage VDD reaches the predetermined voltage. Thus, it is difficult for the low voltage detection circuit illustrated in FIG. 7 to output the low voltage detection signal correctly.
An example of such a problem is illustrated in FIG. 9. Note that the input voltage VDD that is required in order for the reference voltage generation circuit to generate the reference voltage Vref shall be V1. That is, if the input voltage VDD is less than or equal to V1, the operation of the reference voltage generation circuit is unstable. In other words, if the input voltage VDD is less than or equal to V1, the reference voltage generation circuit does not output a normal reference voltage (the detection signal indefinite range of FIG. 9). In this case, the low voltage detection signal output by the low voltage detection circuit is indefinite.
The reason that the low voltage detection signal is indefinite is explained hereinafter. As mentioned above, if the input voltage VDD is low, which is less than or equal to V1, the voltage by the input terminal side of the inverter 539 indicates the reference voltage Vref via the resistor 540. However, at low voltage, the correct reference voltage Vref is not supplied from the reference voltage generation circuit, which is provided externally, to the reference voltage terminal 522. Then the voltage by the side of the input terminal of the inverter 539 is indefinite. Therefore, the low voltage detection signal output by the low voltage detection circuit does not operate normally, either.
Especially, even if the input voltage VDD rises relatively quickly at a power on, it often takes time for the reference voltage generation circuit to operate normally. That is, even if the input voltage VDD indicates more than or equal to the detection voltage VOL, the reference voltage generation circuit may not output a normal reference voltage Vref. In this case, there is a problem that the low voltage detection signal does not operate normally until the reference voltage Vref is stabilized.
This problem is explained using an actual electronic circuit. FIG. 10 illustrates a photocurrent-to-voltage conversion circuit used as a receiver circuit of a photocoupler. The circuit illustrated in FIG. 10 is used to electrically isolate between an input and an output of a FA (Factory Automation) related servo control apparatus etc. For example, a light-emitting device of the input side (a light-emitting diode, for example, which is not illustrated in FIG. 10) emits light to a light-receiving device of the output side when an electric signal is supplied. At this time, a current corresponding to the received light flows into the light-receiving device (photodiode, for example). Then, the circuit illustrated in FIG. 10 converts the photocurrent flowing into the light-receiving device (photodiode, for example) into a voltage and outputs it. As for such a photocoupler, a voltage level of the output signal is determined according to whether the light-emitting diode emits light or not. For example, if the light emitting diode emits light, the output voltage V0 indicates a high-level. On the other hand, if the light emitting diode does not emit light, the output voltage V0 indicates a low-level (0V).
The photocurrent-to-voltage conversion circuit illustrated in FIG. 10 is provided with a photodiode 300 for receiving light and generating a photocurrent, and an I/V converter 301 for converting the photocurrent into a voltage. The circuit illustrated in FIG. 10 is further provided with a power supply voltage detection circuit 303 as the one in FIG. 7, a reference voltage source 302, a NAND circuit 304, and an inverter 305. The UV converter 301 is driven by the reference voltage Vref generated by the reference voltage source 302. The I/V converter 301 converts the current flowing in the photodiode 300 into a voltage, and outputs it to one of the input terminal of the NAND circuit 304. The power supply voltage detection circuit 303 outputs the low voltage detection signal to another input terminal of the NAND circuit 304. The NAND circuit 304 outputs the output voltage V0 outside via the INV circuit 305. Although not illustrated, the power supply voltage detection circuit 303 is driven by the reference voltage Vref.
If the power supply voltage VDD is lower than the detection voltage VOL, the power supply voltage detection circuit 303 outputs the low-level low voltage detection signal, for example. Then, the output signal of the I/V converter 301 is not propagated as the output voltage V0 of the photocurrent-to-voltage conversion circuit. That is, the output voltage V0 of the photocurrent-to-voltage conversion circuit is forced to indicate a low-level (0V). On the other hand, if the power supply voltage VDD is higher than the detection voltage VOL, the power supply voltage detection circuit 303 outputs a high-level low voltage detection signal, for example. Then, the output signal of the I/V converter 301 is propagated as an output voltage V0 of the photocurrent-to-voltage conversion circuit. That is, the photocurrent-to-voltage conversion circuit can output the output voltage V0 according to the input light.
An example in case the power supply voltage VDD rises relatively quickly at a power on is illustrated in FIGS. 11A and 11B. As the power supply voltage VDD rises relatively quickly, the reference voltage Vref is stabilized (rises) after the power supply voltage VDD reaches the detection voltage VOL. Note that the horizontal axis indicates time passed since the power on. The vertical axis indicates the voltage. As illustrated in FIGS. 11A and 11B, the reference voltage Vref is not stabilized (has not risen) even at the time when the power supply voltage VDD indicates the detection voltage (t1). Accordingly, the output voltage V0 is not stabilized until the reference voltage Vref is stabilized (from t1 to t2).
For example, as illustrated in FIG. 11A, if light is input to the photodiode 300, the power supply voltage VDD is less than or equal to the detection voltage VOL till the time t1. Then the output voltage V0 indicates a low-level (0V). However, the reference voltage Vref is not stabilized even after the time t1. Therefore, the I/V converter 301 does not operate normally. Further, as the reference voltage Vref is unstable, the low voltage detection signal output from the power supply voltage detection circuit 303 not stabilized either, as described above. Accordingly, the output voltage V0 repeats high-level and low-level until the reference voltage Vref is stabilized (from t1 to t2). That is, so-called “ringing” occurs.
On the other hand, as illustrated in FIG. 11B, even if there is no light input to the photodiode 300, the reference voltage Vref is unstable from the time t1 to t2, thus the I/V converter 301 doesn't operate normally. Further, as the reference voltage Vref is unstable, the low voltage detection signal output from the power supply voltage detection circuit 303 is not stabilized either, as described above. Accordingly, there is a problem such that the output voltage V0 indicates a different signal (for example a high-level signal) from an actual output logic.
A solution to such problem is disclosed in Japanese Unexamined Patent Application Publication No. 2005-278056. FIG. 12 illustrates a power supply voltage drop detection circuit (power supply voltage detection circuit) disclosed in Japanese Unexamined Patent Application Publication No. 2005-278056. The circuit illustrated in FIG. 12 is provided with a reference voltage source 402, switches 407 and 409, a voltage divider 403, a resistor 408, and a comparator 404. The voltage divider 403 includes resistors 410,411. The switches 407 and 409, and the resistor 408 constitute a switching circuit 406. The reference voltage source 402 generates a reference voltage VREF. The switch 407 is controlled to be on and off by the reference voltage VREF. The switch 409 is controlled to be on and off by the on/off state of the switch 407 and the power supply voltage VCC. The voltage divider 403 divides the power supply voltage VCC supplied via the switch 409, and outputs it as an output voltage VS. The comparator 404 compares the reference voltage VREF with the output voltage VS, and outputs a comparison result. Note that the switch 407 is an N-channel MOS transistor, and the switch 409 is a P-channel MOS transistor.
First, a case in which the power supply voltage VCC is low is explained. In this case, the reference voltage VREF output by the reference voltage source 402 is low (approximately 0V). That is, the voltage applied to a control terminal (gate) of the switch 407 has not reached the threshold voltage. Accordingly, both the switches 407 and 409 are turned off. As a result, the output voltage VS of the voltage divider 403 indicates 0V. Thus, the output voltage VOUT of the comparator 404 indicates a high-level, that is, the power supply voltage VCC.
Next, a case in which the reference voltage VREF begins to increase by the increase of power supply voltage VCC is explained. In this case, both the switches 407 and 409 are turned on. As a result, the power supply voltage VCC is applied to the voltage divider 403. However, since the output voltage VS is low compared with the reference voltage VREF, the output voltage VOUT of the comparator 404 indicates a high-level (VCC). However, if the power supply voltage VCC further increases, the output voltage VS also increases along with that. Then, if the output voltage VS becomes higher than the reference voltage VREF, the output voltage VOUT of the comparator 404 indicates a low-level, that is, 0V.
FIG. 13 illustrates the relationship between the power supply voltage VCC, the output voltage VOUT, the reference voltage VREF, and the output voltage VS, in the circuit illustrated in FIG. 12. If the power supply voltage VCC is low (less than or equal to V1), the reference voltage VREF and the output voltage VS indicate a low voltage (about 0V). Therefore, the output voltage VOUT indicates a high-level (VCC). Next, if the power supply voltage VCC increases, the reference voltage VREF rises (is stabilized). The output voltage VS also increases along with that. However, if the power supply voltage VCC is less than or equal to the detection voltage VOL, it is VS<VREF. Then the output voltage VOUT indicates a high-level (VCC). Then, if the power supply voltage VCC further increases, the power supply voltage VCC exceeds the detection voltage VOL. At this time, it is VS>VREF. Then the output voltage VOUT indicates a low-level (0V).
As described so far, based on the detection voltage VOL of the power supply voltage VCC, the output voltage VOUT of the circuit illustrated in FIG. 12 switches from a high-level (VCC) to a low-level (0V). Then the circuit illustrated in FIG. 12 can detect a low voltage state of the power supply voltage VCC. Note that if the reference voltage VREF is not stabilized, the circuit illustrated in FIG. 12 maintains the output voltage OUT to be high-level, even if the power supply voltage VCC reaches the detection voltage VOL. In this way, the circuit illustrated in FIG. 12 detects a low voltage state of the power supply voltage VCC according to the state of not only the power supply voltage VCC but also the reference voltage VREF. This prevents from generating the problem of the circuit illustrated in FIG. 7.